1. Technical Field
The present invention relates, in general, to improved semiconductor devices. In particular, the present invention relates to a configurable self-test for integrated circuit devices.
2. Description of the Related Art
As integrated circuitry has advanced, more and more circuit devices, and consequently more circuits and circuit functions, can be placed on a single silicon wafer microchip. These circuits perform many different functions, and the circuits must be tested before they are utilized in particular products. As integration has increased over time, memory arrays have been incorporated with logic on the same silicon chip. The dense integration of logic circuitry, such as very-large-scale integration (VLSI), on silicon microchips has thus created immense problems for the test engineer. With advancing developments of VLSI semiconductor circuits, the number of circuit elements, such as gates, flip-flops, and memory cells, on an integrated chip, is expanding to very large numbers. This expansion has given rise to increasing problems in testing the chips, both in their original manufacturing test and during their use in the field.
The complexity and cost of test generation and fault simulation increases with an increasing number of circuit elements. It is well known in the art of integrated circuits that test generation and fault simulation cost for a chip grows approximately proportionally to the third power of the number of gates and flip-flops on the chip. Similarly, the length and execution time of tests increase with the increasing complexity of chips. Since the chip manufacturing cost is expected to decrease over time as production increases, the testing cost is a significant portion of the overall chip cost.
In order to manage functional testing of such complex circuitry, a VLSI chip must be divided into independently testable blocks. Defective VLSI circuits can then be screened utilizing a variety of tests. For example, to increase the speed of testing on-chip memory, the input and output (i.e., I/O) of the memory arrays have been multiplexed with primary I/O's so that the tester has direct control of the array inputs and can direct observability of the array outputs. One problem with such a testing approach is that testing of arrays must be performed serially if there are not enough I/O's on the chip to test multiple arrays in parallel. Such a method is expensive and also time consuming, and generally inefficient due to the fact that the chip cannot be tested in parallel. Performance degradation is also an artifact of this type of testing.
To alleviate this costly bottleneck on the tester, the concept of Array Built In Self-Test (ABIST) was introduced. ABIST is specialized logic, implemented on the same silicon with the memory array, designed to detect manufacturing defects in memory arrays. The ABIST logic writes and reads patterns to and from the memory array while incremementing and decrementing through the entire address range. Comparisons are performed after each read of the array to determine if the write and read operations were successful. Miscompares indicate a defect in the memory array silicon.
In previous ABIST testing designs, a separate ABIST testing unit was provided on an integrated circuit for each device sought to be tested. This approach provided the advantage of testing multiple arrays concurrently, such that test time was limited to the time necessary to test the largest memory array at the expense of silicon area taken by each ABIST controller. Thus, a separate ABIST controller was needed for each memory device.
Other ABIST testing designs provided for a single ABIST controller which could be utilized to test a variety of memory devices of varying sizes. However, the single ABIST controller could only be designed and utilized for a specific combination of arrays and fixed array sizes. Such an approach was limited because a mere change in a single array size could render the ABIST controller inoperable.
As integration continues to improve, the utilization of core-plus ASIC (C+A) or "systems-on-silicon" designs, well known in the art of integrated circuit testing, have increased, which in turn has increased the need for design reuse. This is particularly evident in testing designs such as C+A designs that require the utilization of a fixed core that has various sized memory arrays attached as needed for a desired application. However, in such cases, utilizing the older testing approaches discussed above in conjunction with designs such as C+A designs presents difficulties. The method of having separate ABIST controllers for each array wastes silicon area and requires a separate design for each different sized array. The method of providing a single controller for fixed array sizes reduces area but must be redesigned for each different sized combination. The same problems are also evident in non-core plus ASIC designs where time-to-market is an important consideration.
From the foregoing, one can appreciate that a need exists for an ABIST design that can be utilized for testing integrated circuit devices of different sized memory arrays. Such an approach is solved by the invention described herein, a single reusable configurable ABIST controller that can be utilized for testing a variety of different sized memory arrays, either within a fixed core or outside the fixed core.